VHDL implementation of low-power turbo decoder

Abstract

Due to famous mistake revising probability turbo coding is significantly used as a piece of advanced correspondence systems. In this paper different arrangement of turbo decoder with decreased element constrain dissemination is shown. In this changed decoder, standard cell based design using pipeline logarithm-most extreme a back (Log-MAP) calculation with clock gating and variable number of cycle is used to reduce the territory and to expand the throughput. Proposed design of modified log-outline decoder is mimicked and mixes using Xilinx14.2. Outcomes of the proposed low-control balanced log-MAP decoder are better than the customary log-MAP turbo decoder.