Data dependent precharging dynamic chain architecture for low power end high speed adders

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI:10.1109/ASIC.1997.617000

W. Paik, In-Chul Hwang, Jae-Wan Kim, S. Kim

引用次数: 1

Abstract

This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the 'precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.

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基于数据的低功耗高速加法器预充动态链结构

提出了一种基于数据相关预充算法的动态链加法器。它抑制了在“预充”模式下由于输出无条件预充而产生的虚假过渡。采用DDP动态链结构设计了64位加法器。仿真结果证实，在3.3 V电源下，其工作频率为270 MHz，功耗为0.105 mW/MHz。它在不降低速度的情况下减少了36%的功率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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