Design of Low Power PMOS Biased Sense Amplifier Using Lector Approach

Abstract

Sense Amplifiers plays an important role in memory circuits. These are fundamentally applied in volatile memory cells. Two new circuits of PMOS biased Sense Amplifier are proposed in the paper. This amplifier has low power dissipation, sense delay and more output impedance [1]. This proposed circuit carry out almost all operations like in conventional circuits however with lower power dissipation and Sense Delay by using LECTOR approach in power gating techniques. The proposed Sense Amplifier overall execution have been simulated and examined using Tanner EDA by employing 180nm technology file.