An efficient architecture of 8-bit CMOS analog-to-digital converter

Abstract

An 8-bit CMOS analog-to-digital converter (ADC) has been designed using a more efficient architecture. The simplified multistep 8-bit ADC requires two 4-bit full-flash cycles by using a modified 4-bit full-flash ADC with a voltage estimator. The speed of this new architecture is similar to conventional half-flash ADC but the die area consumption is much less due to reduced numbers of comparators and resistors.