A 10-Bit 50-MSPS Pipelined CMOS ADC

Abstract

This paper presents a 10-bit 50-MSPS pipelined ADC targeted to 0.35 um CMOS technology. The main characteristics of pipelined ADC such as signal to noise and distortion ratio (SNDR), spurious free dynamic range (SFDR), differential non-linearity (DNL), integral non-linearity (INL) and power consumption are simulated in HSPICEreg. In this simulation, a full-scale of Nyquist-frequency sine-wave input is used. The results show the designed pipelined ADC achieves a SNDR of 58 dB, SFDR of 70 dB, maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 0.5 least significant bit (LSB) and a power consumption of 350-mW.