Measurements of an EMC test chip for lower EME in CMOS digital circuits

Abstract

In digital designs, it becomes more and more important to reduce the supply current variations (di/dt noise) they induce in the supply lines. This is due to the fact that steep variations in supply current give rise to EM (electro-magnetic) emission. Hence, integrated circuits with lower emission are greatly demanded, especially in the automotive market. This paper describes several efficient low EME design techniques. Based on a 0.35 mum CMOS EMC test chip, the effectiveness of emission reduction techniques is quantified through a set of measurements.