Performance analysis of multi-VT design solutions in 28nm UTBB FD-SOI technology

Abstract

UTBB FD-SOI technology is able to reach very high speeds thanks to flip-Wells variant which enables low-VT (LVT) tuning. This approach appears to be the best design option to catch high CPU frequencies or/and optimal energy consumption. To save power when logical paths are not critical, regular-VT (RVT) transistors, which seat on classical-Wells, cannot be abutted to LVT transistors because of the Well bias conflicts. To overcome these multi-VT constraints, several innovative cointegration schemes based on single-Well (SW) approaches have been designed in 28nm UTBB FD-SOI technology and validated by silicon results.