Dynamic flip-flop with improved power

Abstract

An improved design of a dynamic flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and improves power-delay product for about 27%, while preserving logic embedding property. This is accomplished by equalizing the t/sub pLH/ and t/sub pHL/ of the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.