Verilog-A Model for a Switched-Capacitor DC-DC Converter

Abstract

This paper presents the development and validation of a Verilog-A behavioral model for a switched capacitor DC-DC converter. For each converter component block, a behavioral model was created and validated, comparing simulation results with the correspondent transistor level implementation. The model was developed to allow the control of the switches ON resistance and dead time between operation phases. Using the behavioral model, the impact on the output voltage ripple amplitude of the switches RON, dead time, capacitors ESR and output track parasitic resistance was evaluated.