First demonstration of vertical Ga2O3 MOSFET: Planar structure with a current aperture

Abstract

β-Ga2O3 is being actively pursued for power devices owing to its wide bandgap of 4.5 eV and the availability of melt-grown native substrates for high quality epitaxy. Depletion and enhancement mode Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETS) reported to date have been implemented as lateral devices. For high voltage and high power ratings, vertical topologies are preferred since chip area utilization is more efficient and device operation is insensitive to surface effects. This paper presents the first experimental demonstration of a vertical Ga2O3 MOSFET, wherein the source was electrically isolated from the drain by a current blocking layer (CBL) except at an aperture opening through which drain current (IDS) was conducted [1]. Modulation of IDS was effected by gating a channel above the CBL. Similar to Si and SiC technologies, this planar device structure was fabricated with no regrowth steps. The buried CBL, which acted as a back barrier for the channel, was formed by Mg-ion (Mg⁺⁺) implantation doping in light of the anticipated deep acceptor nature of Mg in β-Ga2O3. Despite large source-drain leakage due to an unoptimized CBL, successful transistor action was realized.