Analysis of Si, InAs, and Si-InAs tunnel diodes and tunnel FETs using different transport models

Abstract

This paper presents a TCAD study on the performance of Si, InAs, and Si-InAs tunnel diodes and tunnel FETs. Comparative NEGF simulations of short InAs homo-diodes and experimental data on Si homo-diodes serve to calibrate the tunnel models for InAs and Si. Two workarounds for the case of Si-InAs hetero devices are found which give similar results. The crucial difference between in-junction and off-junction band-to-band tunneling is pointed out. Whereas the former cannot yield a sub-thermal slope, the latter can eventually produce a point slope of 25 mV/dec, albeit at extremely small current levels. The TCAD prediction for the maximum on-current of a Si-InAs hetero TFET is 3e-6 A/µm, about 3 orders of magnitude less than world-record CMOS.