Power efficient realtime super resolution by virtual pipeline technique on a server with manycore coprocessors

K. Ishizaka, Takamichi Miyamoto, S. Akimoto, A. Iketani, T. Hosomi, J. Sakai
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Abstract

Super Resolution image processing (SR) is a heavy task for a today's mid-range Xeon server. To accelerate SR, we utilize a server system with manycore coprocessor, Intel Xeon Phi coprocessor. Function offload model is a usual execution model for those systems. However it is difficult for SR to increase utilization of both host processors and coprocessors by the model. We propose a virtual pipeline model which can fully utilize both processors. Experimental results show that our SR improves performance 3.3 times and performance/watt 1.5 times. Our SR achieves 30 frames per sec from SD to HD.
在多核协处理器服务器上,采用虚拟流水线技术实现高效节能的实时超分辨率
对于今天的中档至强服务器来说,超分辨率图像处理(SR)是一项繁重的任务。为了加速SR,我们使用了一个多核协处理器的服务器系统,Intel Xeon Phi协处理器。函数卸载模型是这些系统常用的执行模型。然而,SR很难通过该模型同时提高主处理器和协处理器的利用率。我们提出了一个可以充分利用两个处理器的虚拟流水线模型。实验结果表明,该方法的性能提高了3.3倍,每瓦性能提高了1.5倍。我们的SR从标清到高清达到每秒30帧。
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