An economic method for fabrication sub-quarter-/spl mu/m gate doped-channel FET's by photolithography

S. Tan, W.T. Chen, M. Chu, W. Lour
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Abstract

This paper reports a new sub-0.5-/spl mu/m gate-length FET processing technique by using conventional i-line optical lithography. The key methodology is to thermally re-flow the patterned photo-resist upon two-step spin-coated SOG. According to this new process, the deposited gate metal has its final length and thickness be separately determined by taped resist profile and SOG thickness. The implemented gate length is as short as 0.41 /spl mu/m. Then it was successfully applied to fabrication of a newly designed hetero-doped-channel field-effect transistor with digital-graded In/sub x/Ga/sub 1-x/As multi-layer forming a HEMT-like channel. This digital-graded In/sub x/Ga/sub l-x/As channel by changing x values from 0.1 to 0.2 has most electrons be closer to gate metal. The measured sheet carrier density and mobility are 4.3 /spl times/ 10/sup 12/ cm/sup -2/ and 3560 cm/sup 2/V/sup -1/s/sup -1/ while the peak carrier concentration is larger than 1 /spl times/ 10/sup 19/ cm/sup -3/. A fabricated 0.41 /spl times/ 100 /spl mu/m/sup 2/ HDCFET exhibits the maximum transconductance of 370 mS/mm with an output current lager than 535 mA/mm and ft (f max) of 26 (32) GHz.
采用光刻技术制备亚四分之一/spl μ m栅极掺杂沟道场效应晶体管的经济方法
本文报道了一种利用传统的i线光刻技术加工小于0.5 μ m /spl μ m栅极场效应管的新技术。关键的方法是在两步自旋涂覆SOG上热再流动图案光阻。根据这种新工艺,沉积的栅极金属的最终长度和厚度分别由胶带抗蚀剂轮廓和SOG厚度决定。所实现的栅长仅为0.41 /spl mu/m。然后成功地将其应用于新设计的异质掺杂沟道场效应晶体管的制作中,该晶体管采用数字渐变的In/sub x/Ga/sub 1-x/As多层结构形成类似hemt的沟道。通过改变x值从0.1到0.2,这种数字渐变的In/sub x/Ga/sub l-x/As通道使大多数电子更靠近栅极金属。测得的载流子密度和迁移率分别为4.3 /spl倍/ 10/sup 12/ cm/sup -2/和3560 cm/sup 2/V/sup -1/s/sup -1/,载流子浓度峰值大于1/ spl倍/ 10/sup 19/ cm/sup -3/。制作的0.41 /spl倍/ 100 /spl μ /m/sup 2/ HDCFET的最大跨导为370 mS/mm,输出电流大于535 mA/mm, ft (fmax)为26 (32)GHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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