Daiki Ogata, R. Kamiya, Yusuke Toyoshima, K. Ohhata
{"title":"A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase Averaging","authors":"Daiki Ogata, R. Kamiya, Yusuke Toyoshima, K. Ohhata","doi":"10.1109/APCCAS55924.2022.10090266","DOIUrl":null,"url":null,"abstract":"This paper proposes a high-time-resolution time to digital converter (TDC) using a coupled ring oscillator (CRO) with phase averaging. The CRO can generate short time interval multiphase clocks, and combining it with a counter enables a high-time-resolution TDC with a wide input range and relatively small circuitry. In addition, the application of phase averaging to the CRO reduces the timing error due to mismatch. A novel sampling technique is also proposed to eliminate the sampling error due to counter delay and glitches. Post-layout simulations were performed on a 10-bit TDC in 28-nm CMOS technology to evaluate the performance of the proposed TDC. The results showed that the high time resolution of 2.5 ps and low power dissipation of 15.6 m W at the sampling frequency of 350 MHz could be obtained, along with the FOM of 0.083 pJ/conv.-step.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"529 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090266","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper proposes a high-time-resolution time to digital converter (TDC) using a coupled ring oscillator (CRO) with phase averaging. The CRO can generate short time interval multiphase clocks, and combining it with a counter enables a high-time-resolution TDC with a wide input range and relatively small circuitry. In addition, the application of phase averaging to the CRO reduces the timing error due to mismatch. A novel sampling technique is also proposed to eliminate the sampling error due to counter delay and glitches. Post-layout simulations were performed on a 10-bit TDC in 28-nm CMOS technology to evaluate the performance of the proposed TDC. The results showed that the high time resolution of 2.5 ps and low power dissipation of 15.6 m W at the sampling frequency of 350 MHz could be obtained, along with the FOM of 0.083 pJ/conv.-step.