Seungwoo Rho, Jieun Choi, Geunchul Park, Chanyeol Park
{"title":"Performance Analysis of Various Multi-and Many-Core Systems Centered on Memory","authors":"Seungwoo Rho, Jieun Choi, Geunchul Park, Chanyeol Park","doi":"10.1109/FAS-W.2019.00053","DOIUrl":null,"url":null,"abstract":"Herein, we evaluated and analyzed the major benchmark performance of various multiple-core systems to identify their structures and characteristics. To this end, we developed a benchmark automation tool and selected five Intel and AMD systems. We also chose three key benchmarks, namely STREAM, High-Performance Linpack (HPL), and High-Performance Conjugate Gradient (HPCG), to evaluate the memory, CPU, and aggregate performance. In the STREAM experiment, the high-bandwidth memory (MCDRAM) performance of the KNL was reduced by more than 50% at a specific point owing to the accuracy of the input array size which can be ignored in DDR memory. In the HPL experiment, KNL using MCDRAM exhibited the best optimization performance, but in the experiment without optimization, the performance of MCDRAM was rather lower than DDR or cache. Thus, MCDRAM code optimization may be required to utilize MCDRAM at peak performance in the many-core environment. In the HPCG experiment, the performance variance was large depending on the combination of the MPI process and the number of shared threads. When the number of MPI processes is set to 2 or 4 and the total number of shared threads is equal to the number of physical cores in the system, excellent performance was obtained. Moreover, the maximum performance of each single system was proportional to the memory performance.","PeriodicalId":368308,"journal":{"name":"2019 IEEE 4th International Workshops on Foundations and Applications of Self* Systems (FAS*W)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 4th International Workshops on Foundations and Applications of Self* Systems (FAS*W)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FAS-W.2019.00053","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Herein, we evaluated and analyzed the major benchmark performance of various multiple-core systems to identify their structures and characteristics. To this end, we developed a benchmark automation tool and selected five Intel and AMD systems. We also chose three key benchmarks, namely STREAM, High-Performance Linpack (HPL), and High-Performance Conjugate Gradient (HPCG), to evaluate the memory, CPU, and aggregate performance. In the STREAM experiment, the high-bandwidth memory (MCDRAM) performance of the KNL was reduced by more than 50% at a specific point owing to the accuracy of the input array size which can be ignored in DDR memory. In the HPL experiment, KNL using MCDRAM exhibited the best optimization performance, but in the experiment without optimization, the performance of MCDRAM was rather lower than DDR or cache. Thus, MCDRAM code optimization may be required to utilize MCDRAM at peak performance in the many-core environment. In the HPCG experiment, the performance variance was large depending on the combination of the MPI process and the number of shared threads. When the number of MPI processes is set to 2 or 4 and the total number of shared threads is equal to the number of physical cores in the system, excellent performance was obtained. Moreover, the maximum performance of each single system was proportional to the memory performance.