Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI:10.1109/ESSCIRC55480.2022.9911449

Meizhi Wang, Sirish Oruganti, Shanshan Xie, Raghavan Kumar, S. Mathew, J. Kulkarni

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Abstract

In this work, we demonstrate a novel unique design approach specifically targeting improved resilience against the fine-grained electromagnetic (EM) side-channel analysis (SCA) attacks. Fine-grained EM SCA captures high SNR EM signature with tiny probes (1mm diameter) compared to coarse-grained EM (∼10mm diameter), making it more potent and leading to a higher threat. The EM-SCA critical circuit blocks are voltage-stacked to share a current loop, and a push-pull voltage regulator (VR) balances the mismatch current between the two stacked blocks. Dataflow and current loops are spatially and temporally randomized to obscure the EM side-channel signatures. Measurement results from a 128-bit Parallel Advanced Encryption Standard (AES) core fabricated in 65nm CMOS shows MTD improvement of 1507X for fine-grained EM SCA. Coarse-grained EM and Power SCA MTDs also show an improvement of 122X and 657X respectively, which may be improved further by combining prior reported SCA resilient techniques.

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具有堆叠电压域和时空随机电路块的弹性安全AES核的细粒度电磁侧信道分析

在这项工作中，我们展示了一种新颖独特的设计方法，专门针对提高对细粒度电磁(EM)侧信道分析(SCA)攻击的弹性。与粗粒度EM(直径~ 10mm)相比，细粒度EM SCA使用微小探针(直径1mm)捕获高信噪比EM特征，使其更有效并导致更高的威胁。EM-SCA关键电路模块电压堆叠以共享电流回路，推挽式稳压器(VR)平衡两个堆叠模块之间的不匹配电流。数据流和电流环在空间和时间上随机化，以模糊EM侧通道特征。采用65nm CMOS工艺制作的128位并行高级加密标准(AES)核心的测量结果表明，细粒度EM SCA的MTD提高了1507X。粗粒度的EM和Power SCA mtd也分别显示出122X和657X的改进，通过结合先前报道的SCA弹性技术可以进一步改进。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

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