A reconfigurable RTOS with HW/SW co-scheduling for SOPC

Abstract

Emerging reconfigurable hardware, SOPC (system on programmable Chip), requires a RTOS to reuse the abundant source code. This paper presents a RTOS with the ability to co-schedule HW/SW, and discusses its architecture in detail for SOPC. The paper addresses an efficient run-time partitioning algorithm for block partitioning of FPGA. At last, a case study will be presented to validate our approach. The RTOS can decreases NRE costs and facilitates integrating hardware and software seamlessly.