T. Takada, Y. Shimazu, K. Yamasaki, M. Togashi, K. Hoshikawa, M. Idda
{"title":"A 2 Gb/s Throughput GaAs Digital Time Switch LSI Using LSCFL","authors":"T. Takada, Y. Shimazu, K. Yamasaki, M. Togashi, K. Hoshikawa, M. Idda","doi":"10.1109/MCS.1985.1113649","DOIUrl":null,"url":null,"abstract":"A GaAs four channel digital time switch having a 2.0 Gb/s throughput is developed. Low Power Source Coupled FET Logic (LSCFL) and 0.55 µm gate length buried p-layer SAINT-FETs are applied. The switch includes 1176 devices (FETs, diodes, and resistors). The 75 % fabrication yield is attained using dislocation free wafers.","PeriodicalId":231710,"journal":{"name":"Microwave and Millimeter-Wave Monolithic Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microwave and Millimeter-Wave Monolithic Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCS.1985.1113649","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A GaAs four channel digital time switch having a 2.0 Gb/s throughput is developed. Low Power Source Coupled FET Logic (LSCFL) and 0.55 µm gate length buried p-layer SAINT-FETs are applied. The switch includes 1176 devices (FETs, diodes, and resistors). The 75 % fabrication yield is attained using dislocation free wafers.