Two-dimensional bandgap engineering in a novel Si-SiGe pMOSFET with enhanced device performance and scalability

Abstract

Two-dimensional device simulations are used to explore the applications of bandgap engineering in improving device performance and scalability. Heterojunction pMOSFETs with strained SiGe in the source and/or drain have substantially suppressed short-channel effects, including field-induced barrier lowering in the devices with high-k gate dielectrics/spacers. Despite the source-side velocity overshoot, the drive currents in these devices are reduced due to the hetero-barriers in the channel. This drawback can be eliminated by the use of a thin Si or SiGe cap layer. Finally, a novel pMOSFET with a SiGe source/drain and a SiGe quantum well channel is proposed. It has reduced SCE and enhanced drive current.