{"title":"Matrix processors using p-ADIC arithmetic for exact linear computations","authors":"E. V. Krishnamurtht","doi":"10.1109/ARITH.1975.6156994","DOIUrl":null,"url":null,"abstract":"A unique code (called Hensel's code) is derived for a rational number, by truncating its infinite padic expansion. The four basic arithmetic algorithms for these codes are described and their application to rational matrix computations is demonstrated by solving a system of linear equations exactly, using the Gaussian elimination procedure. A comparative study of the computational complexity involved in this arithmetic and the multiple prime module arithmetic is made with reference to matrix computations. On this basis, a multiple padic scheme is suggested for the design of a highly parallel matrix processor.","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1975.6156994","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
A unique code (called Hensel's code) is derived for a rational number, by truncating its infinite padic expansion. The four basic arithmetic algorithms for these codes are described and their application to rational matrix computations is demonstrated by solving a system of linear equations exactly, using the Gaussian elimination procedure. A comparative study of the computational complexity involved in this arithmetic and the multiple prime module arithmetic is made with reference to matrix computations. On this basis, a multiple padic scheme is suggested for the design of a highly parallel matrix processor.