Research and implement a low-power configurable embedded processor for 1024-point fast fourier transform

Abstract

The embedded processors need to be efficient in order to achieve real-time requirements with low power consumption for specific algorithms. Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In TTA processors, the special function units can be utilized to increase performance or reduce power dissipation. This paper presents a low-power TTA processor using hybrid asynchronous and synchronous function units. This processor is customized for a 1024-point FFT application. We also implement a processor only using synchronous function units. Comparing to the synchronous processor core, the processor core using asynchronous function units has lower average power dissipation and higher performance.