Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns

Abstract

Fault injection in circuit level has proved to be cumbersome and time-consuming when employed to characterize the soft error sensitivity of digital circuits, hence new generation of CAD tool is required to automate the faults insertion and the validation of soft error mitigation mechanisms of the circuits. This paper outlines the characteristics of a new fault-injection platform HSECT-SPI (HIT Soft Error Characterization Toolkit-Spice Based) and its evaluation in some benchmark circuits implemented with distinct processes and soft error hardening techniques. It also details some techniques devised and implemented within the platform to automate and speed-up the circuit level fault-injection experiments. Experimental results are provided, showing that the platform is efficient, accurate and can direct the design of soft error immune circuits with at least three orders of magnitudes speed gain.