A processing engine for GPS correlation

2010 IEEE 8th Symposium on Application Specific Processors (SASP) Pub Date : 2010-06-13 DOI:10.1109/SASP.2010.5521149

A. El-Rayis, T. Arslan, A. Erdogan

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引用次数: 2

Abstract

The correlation process in direct sequence spread spectrum (DSSS) communication systems is key in having successful signal reception. The implementation of real-time correlation in digital signal processors is one of key challenge in the realization of positioning systems today; as a result, most realizations are either application specific integrated circuits (ASIC) or Field Programmable Gate Array (FPGA) based. In this work we have introduced a new correlation engine targeting performance critical Global Positioning Satellite (GPS) based positioning. The processor is based on Reconfigurable Instruction Cell Array (RICA) paradigm. The GPS has been chosen due to its extensive integration in handheld devices (e.g. mobile phones) together with rising energy consumption concerns. We have designed, programmed and implemented several time-domain correlator engines based on RICA architectural paradigm. Various optimization techniques were implemented to adapt the processor to the correlation algorithm and in order to achieve the best performance. 12 and 24 channel correlators are tested using the new processor architecture.

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GPS相关处理引擎

直接序列扩频(DSSS)通信系统中的相关处理是保证信号接收成功的关键。在数字信号处理器中实现实时相关是当今定位系统实现的关键挑战之一;因此，大多数实现要么是专用集成电路(ASIC)，要么是基于现场可编程门阵列(FPGA)。在这项工作中，我们介绍了一种新的相关引擎，针对性能关键的全球定位卫星(GPS)定位。该处理器基于可重构指令单元阵列(Reconfigurable Instruction Cell Array, RICA)范式。之所以选择GPS，是因为它广泛地集成在手持设备(如移动电话)中，同时也考虑到日益增长的能源消耗问题。我们设计、编程并实现了几个基于RICA架构范例的时域相关器引擎。为了使处理器适应相关算法并达到最佳性能，采用了各种优化技术。采用新的处理器架构对12通道和24通道相关器进行了测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2010 IEEE 8th Symposium on Application Specific Processors (SASP)

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