Study on the Simulation Method for Universal Serial Bus 2.0 Hard Design Based on SmartModel

Abstract

Universal Serial Bus 2.0 is a kind of new interface technology. It has virtues of high speed, using easily, hot Plug and Play, low-cost, and etc. So it was widely used in all kind of instrumentations and devices, which include personal computers, digital cameras, scanners, joysticks, magnetic tapes, floppy drives, image devises, printers, keyboards, mice, and etc. Universal Serial Bus 2.0 systems consist of USB host control chip and equipment interface control chip, i.e. peripheral device chip. The host control chip was usually integrated in the chip groups of personal computer, its function is single, and some large chip group manufacturers often control its technologies. Therefore the traditional USB developing is only to develop USB peripheral devices, USB peripheral device chips are involved with FIFO and FIFO controller, Direct Memory Access Controller (DMAC), Serial Interface Engine (SIE), USB 2.0 Transceiver Macrocell Interface (UTMI), and etc. These peripheral devices are connected with USB host to achieve all kinds of transactions disposing of USB 2.0. On developing USB 2.0 peripheral device IP core, how to test and verify the correctness of verilog HDL codes of these designed peripheral device chips is a problem that must be solved. Combining with actual project, this paper presents a set of detailed methods which make use of SmartModel tool and some developed tasks to design a test and simulation system for USB 2.0 peripheral devices IP core, proponed methods were involved with circumstance setup, command use, test module design, all kinds of transactions disposing such as IN type, OUT type, SETUP type, SOF type, additional tasks developing, and etc. Simulation results show these methods are valid, so can offer the reference for development of USB 2.0 system in all kinds of instrumentations and devices.