Scaling down a level shifter circuit in 28 nm FDSOI technology

Abstract

In this work, we used a Pareto front based scaling method to reproduce a level shifter circuit in 28nm FDSOI technology. We selected propagation delay, switching energy, static power dissipation and noise margin, to evaluate the circuit performance and optimize the scale down procedure. The final result showed a set of transistor dimensions, which ensured a desired performance of the level shifter circuit in 28nm fully depleted silicon-on-insulator (FDSOI) technology from ST Microelectronics. The circuit can operate correctly for supply voltages from 250 mV to 1V. The propagation delay of the level shifter is 3.11ns and the static power dissipation is 265 pW. The results contain the comparison of the transistor dimensions across different technologies.