Low power units for the Viterbi decoder

Abstract

In this paper, the issues of designing a low power VLSI implementation of the Viterbi decoder are addressed. We propose a new improvement in the VLSI architecture of the Add-Compare-Select unit (ACSU) and the State-Decode Unit (SDU) in the Viterbi decoder. These new schemes have led to a 47.6% and 43.9% power consumption reduction compared to the conventional ACSU and SDU architectures, respectively. These new improvements have also reduced the critical path of both units. The use of these new architectures in the design of a systolic sliding block Viterbi decoder, has led to a reduction of 25.8% in power consumption and 12.2% in die area. A 7.3% gain in decoding rate has also been gained without any degradation in error performance.