Measurement techniques for coupling characterisation inside CMOS integrated circuits

Abstract

In this paper, techniques for crosstalk coupling modelling, simulation and measurement are proposed. A coupling model including capacitance and substrate effects is used for SPICE simulations for a given pair of inverters with varying size ratios and substrate resistivities. A technique is proposed for the measurement of the crosstalk noise based on RS latch sensors. An experimental implementation of the sensors in a 1.0 /spl mu/m CMOS technology is presented and the crosstalk measurements are compared to the simulation predictions. The results show high crosstalk noise close from the commutation point of the logic. Forecasts concerning submicron technologies are presented together with new sensor implementations.<>