Efficient Vedic Signed Digit Decimal Adder

Abstract

Decimal arithmetic is convenient for financial calculations and other database manipulations as compared to binary arithmetic. Research is still going on to have specialized decimal arithmetic hardware processing units to make these tasks more efficient in terms speed, power and hardware to supports these applications. In this paper, we propose a new approach to decimal addition that is simple in concept, appealing and efficient in terms of speed and hardware. The proposed decimal adder utilises a signed 2's complement vinculum representation of the decimal numbers. The design although generates a dual carry, i.e., a positive and a negative carry, analysis of the adder has revealed a much lower probability of carry generation as compared to the conventional decimal adder allowing the possibility of parallel decimal addition. The proposed VBCD adder is tested up to 16-digit on vertex 6 FPGA platform and also on 180 nm Cadence digital Encounter Tools