{"title":"Dual-Band Concurrent Low Noise LNA","authors":"Y. Sawayama, T. Morishita, K. Komoku, N. Itoh","doi":"10.1109/RFIT49453.2020.9226242","DOIUrl":null,"url":null,"abstract":"This paper presents 1.66/3.26 GHz dual-band concurrent LNA with low NF. Proposed LNA incorporates notch filter matching circuit and mutual induction matching circuit on input and output side to improve NF. The measured $S_{11},S_{22},S_{21}$ and NF were −7.11 dB, −8.41 dB, 12.5 dB, and 1.91 dB at 1.66 GHz and −7.52 dB, −16.0 dB, 9.02 dB and 3.25 dB at 3.26 GHz, respectively. IP1dB exhibits −10.3/−4.7 dBm at 1.66/3.26 GHz. The power consumption is 20.5 mW from a 1.8 V supply voltage. The proposed LNA is designed by using the TSMC-180 nm CMOS process.","PeriodicalId":283714,"journal":{"name":"2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT49453.2020.9226242","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents 1.66/3.26 GHz dual-band concurrent LNA with low NF. Proposed LNA incorporates notch filter matching circuit and mutual induction matching circuit on input and output side to improve NF. The measured $S_{11},S_{22},S_{21}$ and NF were −7.11 dB, −8.41 dB, 12.5 dB, and 1.91 dB at 1.66 GHz and −7.52 dB, −16.0 dB, 9.02 dB and 3.25 dB at 3.26 GHz, respectively. IP1dB exhibits −10.3/−4.7 dBm at 1.66/3.26 GHz. The power consumption is 20.5 mW from a 1.8 V supply voltage. The proposed LNA is designed by using the TSMC-180 nm CMOS process.