Underlap DGMOS for ultra-low power digital sub-threshold operation

Abstract

Inthis paperwe analyze theimpact ofgateunderlap on theeffective capacitance ofDoubleGateMOS (DGMOS) transistor fordigital sub-threshold operation. Results onaring oscillator showthat withoptimum underlap 40%improvement indelay canbeachieved with7.3Xreduction inpowerdelay product (PDP). I.Introduction Sub-threshold leakage current canbeusedinapplications requiring ultra-low powerconsumption withlowtomedium (tentohundreds ofmegahertz) frequency ofoperation [1], e.g.cellphones, PDA,pacemaker etc.DoublegateMOS (DGMOS)transistors aresuitable forsub-threshold operation (VDD < VTH(Fig. 1)) duetotheir nearideal sub-threshold slope andnegligible intrinsic capacitance [2]. Inthis paper we investigate theeffectiveness ofthegateunderlap inDGMOS device forfurther minimizing powerconsumption indigital sub-threshold operation. Unlike super-threshold operation, the intrinsic capacitance oftheDGMOS operated inthesubthreshold region isnegligible andisveryweakly dependent onthechannel length [2]. Hence, theeffective capacitance (CG) inthesub-threshold region isdominated bytheparasitic capacitance. We showthat withoptimum gateunderlap the parasitic capacitances ofDGMOScanbesignificantly reduced, whichinturn leads tolower circuit powerconsumption.