Nano-scale MOSFETs with programmable virtual source/drain

Abstract

In this work, we fabricated twin silicon-oxide-nitride-oxide-silicon (SONOS) memory (TSM) cell transistors, based on the 90 nm non-volatile memory technology and showed the implementation of programmable threshold voltage (V/sub th/) MOSFETs in the nano-scale regime. It was clearly observed that the transistor has high I/sub on//I/sub off/ ratio (>106) and small drain leakage (/spl sim/10 pA) in the 30 nm regime. From the experimental result from fabricated devices, it can be deduced that the TSM transistor has various MOSFET applications due to charged states in the nitride. To evaluate the various MOSFET applications of the TSM transistor in the nano-scale regime, the simulation of a 30 nm-long gate TSM transistor was carried out on the 2D ATLAS, including tunneling and impact ionization models. It is concluded that the proposed TSM MOSFET structure promises a well-controlled short channel effect and high I/sub on//I/sub off/ characteristics.