Bridging the gap between complex software paradigms and power-efficient parallel architectures

Abstract

Achieving extreme-scale computing requires power-efficiency of the computing elements. Power efficiency is usually achieved by cutting transistor budget from hardware structures that exploit locality such as caches and replacing them with software-managed local-store to maintain performance; it can also require removing hardware structures that exploit instruction level parallelism that is not well expressed in software, such as out-of-order execution units - leaving support only for vector execution units. Power efficiency generally leads to complicating software development. Heterogeneous systems provide a tradeoff that combines complex processor cores with power-efficient accelerators to handle multiple code types.