AN IEEE 1149.1 BASED LOGIC/SIGNATURE ANALYZER IN A CHIP

Abstract

This paper describes an IEEE 1149.1 based test IC that emulates the functions of logic and signature analysis test instruments. These ICs can be used at the board or multi-chip module level t o provide an embedded method of monitoring circuits at-speed. This a er assumes the reader has a basic understanding o t t f e IEEE 1149.1 ~ t a n d a r d c ~ , ~ ~ . INTRODUCTION Test instruments, such as logic analyzers, have traditionally been used t o test the at-speed interaction of functioning ICs on board designs. These tes t instruments gain access t o the circuit under test by physically contacting the circuit using a probing mechanism. The use of these test instruments t o test functioning circuitry can reveal timing sensitive and/or intermittent failures that would otherwise not be detectable in a nonfunctional test environment. The abilit of these test instruments t o s nchronize up with and o%serve the at-speed operation o f electronic circuits, have made them an invaluable asset in a wide range of testing applications. With the increasing use of high-speed, state-of-the-art integrated circuits in combination with the miniaturized substrates on which they are assembled, the physical access between an external test instrument and a circuit under test is being severely reduced and in some cases com letely eliminated. New test approaches such as the IEEE 1149.1 boundary scan standard provide a method t o regain electrical access t o miniaturized circuits and substrates through the use of an IC resident test ort and boundary scan architecture. The 1149.1 stanfard provides an excellent method of testing the structural integrity of the wiring interconnects between ICs on a common substrate 3,41. In addition, 1149.1 can be used to test individual Ids while they are in a nonfunctional mode. However, the 1149.1 standard cannot be used effectively for at-speed functional testing of ICs or circuits. The standard does provide a test instruction, referred t o as SamplePreload, that allows the boundary scan register t o take a snapshot sample of the data entering and leaving a functioning IC. While a s ecific application of the SampleRreload instruction has teen describedlg, its general use suffers due to problems not addressed in the standard[,]. One problem with the SamplefPreload instruction is that there is no prescribed method of synchronizing the sample operation with the operation of the host IC. Sampling data asynchronously is a hi t and miss proposition that serves no useful purpose. Another problem is that there is no prescribed method of ualifying when t o execute the sample operation in a P unctioning system. Sampling data synchronously but at random does little t o support testing. The solutions t o these potentially challenging problems is left up to the user of 1149.1. A new a proach, therefore, is required to provide a method o!functionally testing the at-speed operation of miniaturized electronic circuits. The approach described in this paper overcomes the loss of functional test access to state-of-the-art circuitry through the use of an IC designed specifically for ermbedded at-speed testing applications. This test IC is a member of TIS SCQPEtm family of testability components and is referred t o as a Digital Bus Monitor (DBdj'. The DBM can be implemented in board or multi-chip module designs and cou led t o critical functional IC bus signals to provide a mehod of non-intrusively monitoring the functional operation of the circuit. When the DBM is enabled via serial in ut from the 1149.1 test bus, it synchronizes up with t%e functional circuitry t o perform data trace and/or data com action on the at-speed data flow between the functionafICs of the circuit. Following the test, the trace data and/or signature collected can be accessed via the 1149.1 test bus for processing. The advantage offered by the DBM is that it enables the use of traditional at-speed test approaches without having to hysically probe the electronic circuit being tested. d o , since the D13Ms are embedded in the product and accessible via the 1149.1 test bus, the tests they provide are reusable throughout the life cycle of the product. For exam le the DElMs can be used for at-s eed testing of the projuct at the assembly site, then fater reused during other phases of the products life cycle such as; hardwarehoftware integration and debug, at-speed system testing, environmental chamber testing, and field testing and diagnostics.