Lead On Chip TSOP Assembly Process For Fast Sram With Peripherally Located Bond Pads

Abstract

Plastic IC encapsulation utilizing Lead On Chip (LCC) die attach is ar1 emerging technology. In applications where a amall package outline is required for large dice with relatively few interconnects, it allows higher device density per unit package area than conventional assembly techniques. Application of I,OC technology for a 4 megabit fast SRAM device assembled in a Thin Small Outline Package (TSOP) is disciussed. The LOC process has been adapted to accommodate peripherally-placed bond pads, via modification of the leadframe design. Because the bonding pads are placed on the periphery of the die rather than centered Zongitudinally on the die surface, the same die can be aasembled with both LOC and conventional technoloqies. Package design, process, and material selection arei discussed. Jntroduct ion A new generation of memory devices is introduced every three years. With each new generation, memory capacity is increased four times and the area of the die is increased one hundred fifty percent.1 Due to limitations in surfacc mount board densities, package sizes have not increa:;ed in size proportionally. Lead on Chip (LOC) , an assembly technology, originally called Area Wire Bond (A-Wire), was developed by IBM to address some of the piroblems associated with having a very large die in a small package.2