Verification Of Error Models Through Low-level Simulation

Abstract

An important issue in fault-injection is the verification of the error models as representative of reahstic errors. One technique to perform this verification involves the injection of faults using a low-level circuit simulator. The errors that are eventually propagated to the chip-pin or higher level level can be considered to be those errors which are most likely to occur, based on those faults. These errors should form the basis for the error models used in higher fault level injection mechanisms.