MOSFET gate open failure analysis in power electronics

Abstract

The compliance to the fault tolerant operation requirement for power electronics is commonly assessed with reference to fault models applicable at component level. For switching MOSFET, the fault models include the short-circuit and open-circuit failures, implicitly assuming that the Gate open failure is equivalent to a switch open or short failure. MOSFET Gate open failure, also called floating Gate failure, may however entail a Drain to Source channel conduction with non-zero impedance and the subsequent power dissipation in the failed device may prove critical because of the thermal failure propagation risk. The present paper is dedicated to that question. It is shown that a power MOSFET with floating Gate is driven by leakage current from whatever initial conduction status either into a steady-state dissipative status or into run-away due to thermal instability. The analysis is confirmed by practical tests. As a conclusion, provisions to mitigate the MOSFET Gate open failure are proposed to be implemented at MOSFET level and/or at converter design level.