Body bias driven design synthesis for optimum performance per area

M. Meijer, J. P. D. Gyvez
{"title":"Body bias driven design synthesis for optimum performance per area","authors":"M. Meijer, J. P. D. Gyvez","doi":"10.1109/ISQED.2010.5450531","DOIUrl":null,"url":null,"abstract":"Worst-case design uses extreme process corner conditions which rarely occur. This costs additional power due to area over-dimensioning during synthesis. We present a new design strategy for digital CMOS IP that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. Dynamic power is reduced depending upon the ratio of flip-flops to logic-gates, and data activity. On a set of benchmark circuits in 65nm LP-CMOS, we observed performance-per-area improvements up to 81%, area and leakage reductions up to 38%, and total power savings of up to 26% without performance penalties.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"28 11","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 11th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2010.5450531","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

Abstract

Worst-case design uses extreme process corner conditions which rarely occur. This costs additional power due to area over-dimensioning during synthesis. We present a new design strategy for digital CMOS IP that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. Dynamic power is reduced depending upon the ratio of flip-flops to logic-gates, and data activity. On a set of benchmark circuits in 65nm LP-CMOS, we observed performance-per-area improvements up to 81%, area and leakage reductions up to 38%, and total power savings of up to 26% without performance penalties.
车身偏置驱动的设计综合,每个区域的最佳性能
最坏情况设计使用很少发生的极端工艺拐角条件。这需要额外的功率,因为在合成过程中面积过大。提出了一种利用前向体偏置的数字CMOS IP设计策略。我们的方法在不牺牲电路性能的情况下,通过限制电路的过尺寸,始终呈现出更好的每面积性能比。动态功率根据触发器与逻辑门的比例和数据活动而降低。在一组65nm LP-CMOS基准电路中,我们观察到每面积性能提高了81%,面积和泄漏减少了38%,总功耗节省了26%,而没有性能损失。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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