Latch-up in Integrated Circuits Under Single and Periodic Electrical Overstress

Abstract

This paper describes the results of sensitivity test to latch-up of several types of ICs (SRAM, EEPROM memory, ADC, microcontroller) caused by single and multiple electrical overstresses. It was shown, that electrical strike with a high-repetition rate increases the sensitivity and vulnerability of ICs to latch-up. The article describes some aspects of the test procedure, which may affect on IC’s sensitivity results.