Proposal and validation of an adaptable array for multi-core processors

Abstract

Reconfigurable architectures have been successfully used as accelerators on single core processor or as stand-alone computer engine. However, on the multi-core era, it is necessary to modify the way as reconfigurable array is used. Traditionally, a set Reconfigurable and Functional Unit are used the same way they are used to single core. Unfortunately, it results on considerable area overhead. Adaptable architectures emerged from the development of reconfigurable architectures. Adaptable architectures are systems able to adapt to applications run on it. This paper proposes and validates an adaptable architecture. A minimal configuration is proposed to accelerate threads from a single core. Also, a configuration to accelerate threads from a multi-core is discussed. Using the minimal configuration the array is able to accelerate 39% the inner loop of a matrix multiplication. Synthetic applications were also used to observe how data dependencies affect the system performance.