{"title":"Quadrature Injection-Locked Frequency Divider ÷2 for Radio Frequency Interference Reduction","authors":"W. Lai, S. Jang, Cheng-Lin Li","doi":"10.1109/IMWS-AMP49156.2020.9199774","DOIUrl":null,"url":null,"abstract":"This article presents a wide-locking range divide-by-2 quadrature injection-locked frequency divider (QILFD) with capacitive cross-coupled oscillator. The ILFD consists of a quadrature voltage-controlled oscillator (QVCO) and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS QILFD has been implemented with the tsmc 0.18-µm CMOS technology and the core power consumption is 20.4mW at the supply voltage of 1V. At the input power of 0dBm, the divide-by-2 locking range is 90.322% from 3.4 GHz to 9.0 GHz. The phase noise of the locked output spectrum is lower than that of free running QILFD in the ÷2 mode for RFI reduction","PeriodicalId":163276,"journal":{"name":"2020 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMWS-AMP49156.2020.9199774","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This article presents a wide-locking range divide-by-2 quadrature injection-locked frequency divider (QILFD) with capacitive cross-coupled oscillator. The ILFD consists of a quadrature voltage-controlled oscillator (QVCO) and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS QILFD has been implemented with the tsmc 0.18-µm CMOS technology and the core power consumption is 20.4mW at the supply voltage of 1V. At the input power of 0dBm, the divide-by-2 locking range is 90.322% from 3.4 GHz to 9.0 GHz. The phase noise of the locked output spectrum is lower than that of free running QILFD in the ÷2 mode for RFI reduction