H. Hoenigschmid, A. Frey, J. DeBrosse, T. Kirihata, G. Mueller, G. Daniel, G. Frankowsky, K. Guay, D. Hanson, L. Hsu, B. Ji, D. Netis, S. Panaroni, C. Radens, A. Reith, D. Storaska, O. Weinfurtner, J. Alsmeier, W. Weber, M. Wordeman
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引用次数: 0
Abstract
A 7F/sup 2/ DRAM cell and corresponding vertically folded bitline architecture has been fabricated using a 0.175 /spl mu/m CMOS technology. This concept features an advanced 30/spl deg/ tilted array device layout and an area penalty free inter BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals.
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