Low voltage SRAM design using tunneling regime of CNTFET

Abstract

This paper presents low-voltage techniques for static random access memory (SRAM) bit-cell design using the ambipolar characteristics of Carbon Nanotube field effect transistor (CNTFET). The sub-60mV/dec band-to-band tunneling (BTBT) leakage region is used for transistor operation which reverses the charging-discharging characteristics of p-type and n-type CNTFETs compared to the conventional CMOS transistors. Our first 8T-SRAM design, operating at 0.33V power supply, has 6 p-type and 2 n-type CNTFETs, all operating in BTBT region. The second design uses all p-type CNTFETs for reliable fabrication process. The proposed SRAM bit-cells have 4 orders of magnitude lower standby leakage current, about 40% wider write margins and ~50% improved read static noise margins compared to state of the art 22nm CMOS bit-cell under an equal SRAM bit-cell area constraint.