{"title":"Transient and permanent fault diagnosis for FPGA-based TMR systems","authors":"S. D'Angelo, G. Sechi, C. Metra","doi":"10.1109/DFTVS.1999.802900","DOIUrl":null,"url":null,"abstract":"In this paper we propose a hardware scheme to allow the diagnosis of transient and permanent faults affecting a Triple Modular Redundancy (TMR) system implemented by means of Field Programmable Gate Arrays (FPGAs). Our scheme allows us to easily identify whether a fault affects one of the replicated modules, the voter, or the scheme itself; and whether such a fault is permanent or transient. Our scheme can therefore be used to drive the selection of the most proper recovery technique for each kind of diagnosed fault. It is suitable to be implemented by means of FPGAs, and has been verified to feature self-checking ability with respect to a wide set of possible internal faults belonging to a realistic set.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"414 7","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"33","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1999.802900","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 33
Abstract
In this paper we propose a hardware scheme to allow the diagnosis of transient and permanent faults affecting a Triple Modular Redundancy (TMR) system implemented by means of Field Programmable Gate Arrays (FPGAs). Our scheme allows us to easily identify whether a fault affects one of the replicated modules, the voter, or the scheme itself; and whether such a fault is permanent or transient. Our scheme can therefore be used to drive the selection of the most proper recovery technique for each kind of diagnosed fault. It is suitable to be implemented by means of FPGAs, and has been verified to feature self-checking ability with respect to a wide set of possible internal faults belonging to a realistic set.