An Energy Efficient CMOS Sub-THz Interconnect with Surface Plasmonic Converter and Oscillator

Abstract

Free-space EM-wave based GHz interconnect suffering significant loss and narrow bandwidth cannot be deployed as low-power and dense I/Os for future network-on-chip (NoC) integration of many-core and memory. This paper proposes an energy-efficient and low-crosstalk sub-THz (0.1T-1T) I/O using surface-plasmonic based interconnects and oscillator in CMOS. By introducing sub-wavelength periodic corrugation structure onto transmission line with gradient groove, the surface-plasmonic is established to propagate signal that is strongly localized on surface of top-layer metal wire. A mode conversion from guided wave to surface wave is carefully designed considering low loss and efficient impedance/momentum matching at mm-wave to THz frequencies. As such, significant power saving and cross-talk reduction can be observed with high communication bandwidth. In addition, a low phase noise surface-plasmonic oscillator with high-Q resonator is also proposed. The phase noise is -116dBc/Hz at 10MHz offset under 0.7V power supply by consuming only 3.5mW power. As designed in 65nm CMOS, the results have shown that the proposed surface-plasmonic I/O interface achieves 25Gbps data rate and 0.01pJ/bit/mm energy efficiency at 140GHz carrier frequency over 20mm dual surface-plasmonic channels.