{"title":"A 6Gbps Serial Link Transmitter with Pre-emphasis","authors":"Chih-Hsien Lin, Chung-Hong Wang, S. Jou","doi":"10.1145/1119772.1119948","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a novel 6Gbps SATA transmitter. The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1-5 meter cable. A test chip of transmitter with PLL and on-chip termination is implemented to verify the design methodology. The overall circuit is implemented in TSMC 0.18 mum 1P6M 1.8 V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68 mW for 6Gbps case.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"300 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1119772.1119948","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
In this paper, we propose a novel 6Gbps SATA transmitter. The transmitter is constructed by PISO, driver, pre-emphasis and PLL for a 1-5 meter cable. A test chip of transmitter with PLL and on-chip termination is implemented to verify the design methodology. The overall circuit is implemented in TSMC 0.18 mum 1P6M 1.8 V CMOS process. The whole measured transmitter jitter is about 44ps and the power consumption is 68 mW for 6Gbps case.