Integration of 100V LDMOS devices in 0.35μm CMOS technology

Abstract

Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm² for N-type LDMOS and RDS (ON) =690/640mΩ.mm² for P-type LDMOS with 14nm/40nm gate oxide thickness.