Investigation of forward body bias effects on TSPC RF frequency dividers in 0.18 μm CMOS

Abstract

Effects of forward body biasing (FBB) is investigated as an effective mean of on-chip scaling of power consumption and operating speed in CMOS true single phase clock (TSPC) RF frequency divide-by-2 circuits. Through extensive dc and RF simulations in 0.18 mum CMOS, the effects of the forward body bias on the threshold voltage, propagation delay, and current dissipation are examined. Then, it is shown that only with the FBB voltage of 0.2 V, the divide-by-2 circuits achieves 22% and 21% improvements in the maximum operating speed while only at the cost of 15% and 32% more current dissipation for TSPC and extended TSPC (E-TSPC) type logics, respectively. We believe that the forward body biasing technique is instrumental in realizing on-chip on-the-fly scalable TSPC dividers for low power applications.