A circuit design for 2 Gbit/s Si brpolar crosspoint switch LSIs

Abstract

A Si bipolar circuit design technology for gigabit-per-second crosspoint switch LSI's is described. An 8X 8 and an expandable 16X 16 crosspoint switch LSI have been developed utilizing a new circuit design and super self-aligned process technology (SST-1A). The LSI's success- fully switched with a bit error rate of less than at 2.5 Gbit/s using a Z9 - 1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 80 ps at 1.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSI's have an ECL-compatible interface, -4- and - 2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8 X 8 LSI and 2.8 W for the expandable 16~ 16 LSI.