Degradation effects in a-Si:H thin film transistors and their impact on circuit performance

Abstract

Amorphous silicon thin film transistors degrade with electrical stress. In particular, the threshold voltage increases significantly with positive gate voltages. The characteristics and mechanisms of the degradation are reviewed. The implications for various types of circuitry including active matrix backplanes, integrated drivers and general purpose digital circuitry are examined. A circuit modeling tool that enables the prediction of complex circuit degradation is presented. Finally, the similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS is discussed along with potential approaches to reducing the degradation effects.