{"title":"Study and mechanism of static scanning laser fault isolation on embed SRAM function fail","authors":"C. Chen, H. Ng, G. Ang, J. Lam, Z. Mai","doi":"10.1109/IPFA.2014.6898202","DOIUrl":null,"url":null,"abstract":"As the technology keep scaling down and IC design becoming more and more complex, failure analysis becomes more and more challenge, especially for static laser analysis. For the foundry FA or process monitoring, SRAM analysis becomes more and more critical. There are two reasons for this: The first one is that SRAM circuit is relative simple which is well known to all, it is also used by fab for monitoring structure. The second reason is the SRAM percentage on-chip keeps increasing. It can occupy more 60% chip area for most logic product. That is also another reason we use the SRAM to monitor our process. SRAM analysis with bit map is relatively easy for FA. But as DFT become more popular, the BIST technical was applied in the SRAM, bit map was provided frequently. The global fault isolation methodology must be employed in the SRAM FA. In this paper, static scanning laser methodology was applied in the SRAM FA which no bit map was provided. Hot spot was observed in the SRAM block edge for some failed units, but some not. Combined with the SRAM schematic and GDS analysis, the defect was successfully found and the failure mechanism was studied, which can successfully link the electrical phenomenon and physical defect. Also, we found the process issue with the FA result.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"47 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2014.6898202","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
As the technology keep scaling down and IC design becoming more and more complex, failure analysis becomes more and more challenge, especially for static laser analysis. For the foundry FA or process monitoring, SRAM analysis becomes more and more critical. There are two reasons for this: The first one is that SRAM circuit is relative simple which is well known to all, it is also used by fab for monitoring structure. The second reason is the SRAM percentage on-chip keeps increasing. It can occupy more 60% chip area for most logic product. That is also another reason we use the SRAM to monitor our process. SRAM analysis with bit map is relatively easy for FA. But as DFT become more popular, the BIST technical was applied in the SRAM, bit map was provided frequently. The global fault isolation methodology must be employed in the SRAM FA. In this paper, static scanning laser methodology was applied in the SRAM FA which no bit map was provided. Hot spot was observed in the SRAM block edge for some failed units, but some not. Combined with the SRAM schematic and GDS analysis, the defect was successfully found and the failure mechanism was studied, which can successfully link the electrical phenomenon and physical defect. Also, we found the process issue with the FA result.